1. Field of the Invention
The invention relates to FIFO devices, and in particular, to a FIFO sharing mechanism for data reproduction.
2. Description of the Related Art
FIG. 1 shows a conventional FIFO system 100 coupled to a first device 115 and a second device 125. The FIFO system 100 comprises a memory controller 120, a CPU 130, a first FIFO device 140 and a second FIFO device 150. The memory controller 120 is controlled by the CPU 130 to access a memory device 110. The first FIFO device 140 serves as an interface for instruction transfer to and from the first device 115, and the second FIFO device 150 for second device 125. The instructions transferred via the first FIFO device 140 and second FIFO device 150, comprise two types, status and data. Status instructions delivered from the first device 115 or second device 125 are parsed and executed by the CPU 130, and data instructions from the first device 115 and second device 125 are sent to the memory device by the memory controller 120. Thus, each of the devices 115 and 125 is simultaneously coupled to the memory controller 120 and CPU 130, with a detection mechanism required determining instruction types stored therein, such that the instructions can be directed accordingly.
FIG. 2a is a flowchart of a conventional data reading process. In step 202, when the FIFO system 100 requests data from first device 115, the CPU 130 initializes the transfer by sending a status instruction to the first FIFO device 140. The first device 115 then reads the status instruction from the first FIFO device 140, and performs an initialization to determine whether the requested data is available. In step 204, a status instruction is delivered from the first device 115 to the first FIFO device 140, indicating the availability of the requested data. Thereafter, the CPU 130 reads the status instruction in the first FIFO device 140. In step 206, if the requested data is available, the first device 115 delivers at least one data instruction carrying the requested data to the first FIFO device 140. Upon confirmation of the availability of the requested data according to the returned status instruction, the CPU 130 commands the memory controller 120 to read the data instruction from the first FIFO device 140 and sends it to the memory device.
FIG. 2b is a flowchart of a conventional data writing process. In step 212, when the FIFO system 100 requests to write data from the memory device to the second device 125, the CPU 130 initializes the transfer by sending a status instruction to the second FIFO device 150. The second device 125 then reads the status instruction from the second FIFO device 150, and performs an initialization to determine whether the second device 125 is capable of storing the data. In step 214, in response, a status instruction is delivered from the second device 125 to the second FIFO device 150, indicating the capability for storage. The CPU 130 reads the returned status instruction in the second FIFO device 150 to confirm the capability. In step 216, upon confirmation of the capability for data storage according to the returned status instruction, the CPU 130 commands the memory controller 120 to deliver the data instruction from the memory device to the second FIFO device 150. In step 218, when the second device 125 obtains the data instruction through the second FIFO device 150, it responds another status instruction as an acknowledgement. Through the second FIFO device 150, the CPU 130 reads the acknowledgement to conclude the data transfer.
The FIFO system 100 may be a card reader, whereas the first device 115 and second device 125 are memory cards such as SECURE DIGITAL (SD) or COMPACTFLASH (CF) cards. SECURE DIGITAL and COMPACTFLASH are standard memory formats and/or trademarks. When there is need to copy data from the first device 115 to the second device 125, or vice versa, the processes shown in FIGS. 2a and 2b are performed. The memory device and CPU 130 occupy significant system resources and time. Additionally, the determination of instruction type also consumes considerable computation power of the CPU 130. A more efficient architecture is thus desirable.